The present invention relates generally to integrated clock circuitry and more particularly to integrated clock circuitry including phase control circuitry in a clock circuit distribution node and/or circuitry connecting the distribution nodes.
As the size and clock frequencies of integrated circuit chips increase, the need to avoid clock skew becomes greater. Integrated circuit chips currently being designed have areas of approximately 48 square micrometers, defined by a square geometry having 20,000 micrometers (i.e., 2 centimeters) on each side. Clock frequencies of such chips frequently exceed 500 megahertz, with the expectation of clock frequencies in the gigahertz range. In addition, power supply voltages for such chips are typically in the range of about 1.3 volts.
These parameters, in combination with integrated circuit processing variations, temperature variations as a function of time and space (i.e., location of circuits on the chip), and voltage variations as a function of time and space result in considerable problems in maintaining synchronization between leading and trailing edges of clock waves distributed to the thousands of components on an integrated circuit chip. The tendency for the leading and trailing edges of the clock waves distributed to different portions of the integrated circuit as a result of the processing, voltage and temperature variations is generally known in the art as skew.
FIG. 1 is a block diagram of a prior art circuit for distributing clock waves (i.e., clock pulse trains) to various parts of an integrated circuit. The circuit of FIG. 1 is generally referred to as a balanced clock tree distribution circuit. The circuit of FIG. 1 has certain deficiencies when used in integrated circuits having the previously defined parameters.
The balanced clock tree distribution circuit of FIG. 1 is essentially an open loop arrangement, all of which is carried on a single integrated circuit chip 10. The clock circuitry of FIG. 1 is driven by bi-level clock source 12 which may be on or external to integrated circuit chip 10 and is connected via suitable terminals and wires (i.e., leads) on the chip to receiver 14. Receiver 14 is generally centrally located on chip 10 and includes plural wires 16 connected to primary buffers 18, spatially distributed about chip 10. Each of primary buffers 18 is connected to plural secondary buffers 20; for convenience, the connections of only one of primary buffers 18 to three secondary buffers 20 are illustrated in FIG. 1. Primary buffers 18 respond to clock waves from receiver 14 to supply clock waves via wires 19 to secondary buffers 20. Secondary buffers 20 respond to the clock waves supplied to them by primary buffers 18 to derive clock waves that wires 24 supply to gater circuits 22. Each gater circuit 22 (not shown in detail) is a clock controlled logic circuit also responsive to sources of binary data (i.e., intelligence representing signals). Gater circuits 22 respond to the clock waves supplied to them by secondary buffers 20 and one or more data signals to produce output signals representing a Boolean logic relation between the clock wave and data signal(s) supplied to the gater. Gater circuits 22 control coupling of the binary intelligence representing signals to further logic circuits on chip 10. Frequently, receiver 14, as well as buffers 18 and 20, include internal feedback circuitry in the form of a phase lock loop for maintaining a predetermined delay time between the clock wave inputs and outputs of these elements; usually, the phase lock loop of each receiver and buffer causes the clock wave input and output of each receiver and each buffer to have simultaneously occurring leading edges and simultaneously occurring trailing edges.
There are several disadvantages with the integrated circuit clock circuitry illustrated in FIG. 1. The clock waves undergo significant routing delay while propagating between the input of receiver 14 and the output of gater circuits 22. The routing delay can exceed the period of one cycle of the clock waves. As a result, the leading edges of the clock waves the different buffers and gaters derive occur at different times, as do the trailing edges of the clock wave.
The circuit of FIG. 1 is also subject to considerable clock skew. Clock skew arises as a result of variations in component values as a function of integrated circuit processing at different parts of the chip. The processing variations cause differential delays of the clock waves at spatially disparate regions of the integrated circuit. In addition, variations in chip temperature and power supply voltage as a function of time and chip location result in significant differential delays in the clock wave leading and trailing edges as a function of time and chip location. For very high clock frequencies e.g., 1 GHz, different circuits on different parts of the chip dissipate considerably different amounts of power as a function of operations performed by the circuits. Transient temperature variations as great as 10xc2x0 C. have been observed. Such variations have a considerable impact on clock wave propagation times. A further problem with the circuit of FIG. 1 is that there are only two phases, displaced from each other by 180xc2x0, available for clock synchronization purposes. In many situations, it is desirable for clock waves to be derived at several (i.e., three or more) phases of a clock source.
It is, accordingly, an object of the present invention to provide new and improved integrated circuit clock distribution circuitry, wherein clock waves derived at disparate locations on an integrated circuit chip have substantially the same phase, or have predictable, stable phase differences.
Another object of the present invention is to provide a new and improved integrated circuit clock distribution circuit, particularly adapted for use on relatively large integrated circuits operating at high clock frequencies, wherein effects of semiconductor processing, as well as temperature and voltage variations as a function of time and/or space are minimized.
Another object of the invention is to provide a new and improved integrated circuit clock distribution circuit, wherein clock waves having several phases, closely synchronized with each other, are derived at substantially the same location on an integrated circuit chip.
An additional object of the present invention is to provide new and improved integrated circuit clock distribution circuitry wherein the lengths of the wires between phase detecting circuitry and delay elements controlled thereby are minimized.
In accordance with one aspect of the present invention, clock circuitry for supplying clock waves to many loads on an integrated circuit chip includes several clock node circuits at different locations on the chip and clock coupling circuitry connected between a clock wave output and input of adjacent clock nodes. Each clock node circuit and the clock coupling circuitry are arranged for maintaining a predetermined phase relation between the clock wave output and input of adjacent clock nodes. The clock node circuits and the clock coupling circuits include a feedback arrangement for maintaining the predetermined phase relation. The clock wave inputs and outputs of the nodes are connected so there is no direct feedback from the clock wave outputs and inputs of any of the different clock nodes.
A feature of the invention is the inclusion of circuitry connected to be responsive to the clock waves at spatially displaced first and second nodes on the chip for (a) comparing the relative phases of the clock waves at the spatially displaced nodes, and (b) deriving a signal indicative of clock skew quality of the chip clock circuitry.
Preferably the signal-deriving circuitry includes: (a) an additional clock node, (b) an additional coupling circuit responsive to a clock wave at the first node, and (c) a phase detector arrangement. The additional clock node responds to a clock wave derived from the additional coupling circuit. The phase detector arrangement responds to a clock wave at the second node and the clock wave output of the additional node to derive the clock skew quality signal.
Another aspect of the invention relates to clock circuitry for supplying clock waves to many loads on an integrated circuit chip, wherein the clock circuitry includes several clock nodes at different locations on the chip and clock coupling circuitry connected between adjacent clock nodes. Each clock node includes (a) a clock wave input, (b) a clock wave output and (c) feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave input and clock wave output of the particular node. The clock coupling circuitry maintains a predetermined phase relation between the output and input of the adjacent clock nodes.
Preferably the feedback circuitry of each node includes a phase detector responsive to clock waves having differing phases within the particular node, and a phase controller (i.e., delay elements in one particular embodiment) responsive to the phase detector of the particular node for controlling the relative phases of the clock waves at the clock wave input and the clock wave output of the particular node. The feedback circuitry of each node has a nominal delay of at least one cycle of the clock wave. The phase detector of each node responds to first and second clock waves having a relative nominal phase of N times one cycle of the clock wave, where N is an integer including one.
In the preferred embodiment, the phase controller of each node includes first and second phase controllers responsive to the phase detector of the node. The first phase controller controls the relative phase delay of a first path in the particular node for coupling the clock waves from the clock input to the clock output of the particular node. The second phase controller controls the relative phase delay of a second path in the particular node for coupling the clock waves from the clock output to the clock input of the particular node.
Each coupling circuit preferably includes a feedback loop having a first path for supplying clock waves from the clock output of the first node to the clock input of the second node and a second path for supplying clock waves from the clock input of the second node to a spatial location on the chip in much closer proximity to the output of the first node than any portion of the second node. The first and second paths have the same delay times causing the clock waves at the output of the first node and at the spatial location to be phase displaced from each other by Pxc3x97360xc2x0/2, where P is an integer including one. A phase detector responsive to the relative phases of the clock waves at the output of the first node and at the end of second path controls the amount of phase delay of the first and second paths of the particular coupling circuit.
A further aspect of the invention concerns clock circuitry for supplying clock waves to many loads on an integrated circuit chip. The clock circuitry comprises several clock nodes at different locations on the chip and clock coupling circuitry connected between a clock wave output and input of adjacent clock nodes. Each clock node includes an arrangement for maintaining a predetermined phase relation between clock waves at the clock wave input and clock wave output of the particular node. Each clock coupling circuit includes a feedback loop for maintaining a predetermined phase relation between the clock wave output of a first of the adjacent nodes and the clock wave input of a second of the adjacent nodes.
In still another aspect of the invention, circuitry responsive to the clock waves at spatially displaced clock nodes on the chip (a) compares the relative phases of the clock waves at the spatially displaced nodes, and (b) derives a signal indicative of clock skew quality of the chip clock circuitry.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.